JDK-8353730 : TestSubNodeFloatDoubleNegation.java fails with native Float16 support
  • Type: Bug
  • Component: hotspot
  • Sub-Component: compiler
  • Affected Version: 25
  • Priority: P4
  • Status: Resolved
  • Resolution: Fixed
  • CPU: x86,aarch64
  • Submitted: 2025-04-04
  • Updated: 2025-07-10
  • Resolved: 2025-04-11
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JDK 25
25 b19Fixed
Related Reports
Causes :  
JDK-8351515 - C2 incorrectly removes double negation for double and float
Duplicate :  
JDK-8354222 - TestSubNodeFloatDoubleNegation intermittently failing
Relates :  
JDK-8345125 - Aarch64: Add aarch64 backend for Float16 scalar operations
Relates :  
JDK-8353665 - RISC-V: IR verification fails in TestSubNodeFloatDoubleNegation.java
Description
The IR test TestSubNodeFloatDoubleNegation.java fails when the machine it is running on has support for Float16. In that case, the compiler generates two half-float subtractions and an alternative codepath with a normal float subtraction. This was first discovered for RISC-V in JDK-8353665, but also applies to x64 with the feature AVX512-FP16 and needs to be investigated for ARMv8 with FEAT_FP16.
Comments
Changeset: efb5a80e Branch: master Author: Manuel Hässig <manuel@haessig.org> Committer: Christian Hagedorn <chagedorn@openjdk.org> Date: 2025-04-11 11:29:56 +0000 URL: https://git.openjdk.org/jdk/commit/efb5a80e52c8314103e1ccec05af6ab480531df0
11-04-2025
A pull request was submitted for review. Branch: master URL: https://git.openjdk.org/jdk/pull/24565 Date: 2025-04-10 08:31:05 +0000
10-04-2025
ILW = Test fails due to unexpected IR (test bug), single test on architectures with FP16 support (AVX512-FP16), no workaround = MLH = P4
07-04-2025