C2 optimizations can lead to execution of integer Div/Mod instructions before the corresponding zero check. Changes were made to prevent this because some CISC architectures (x86, s390) raise SIGFPE when dividing by zero (see related issues).
However, some RISC architectures (PPC64, AARCH64, RISC-V?) don't raise signals and, hence, allow division speculatively before the zero check.
We should check if allowing Div/Mod instructions to float on these architectures is beneficial and possibly adapt the changes which were made for CISC architectures.