JDK-8206163 : AArch64: incorrect code generation for StoreCM
  • Type: Bug
  • Component: hotspot
  • Sub-Component: compiler
  • Affected Version: 8-aarch64,11
  • Priority: P1
  • Status: Closed
  • Resolution: Fixed
  • CPU: aarch64
  • Submitted: 2018-07-02
  • Updated: 2021-02-01
  • Resolved: 2018-07-09
The Version table provides details related to the release that this issue/RFE will be addressed.

Unresolved : Release in which this issue/RFE will be addressed.
Resolved: Release in which this issue/RFE has been resolved.
Fixed : Release in which this issue/RFE has been fixed. The release containing this fix may be available for download as an Early Access Release or a General Availability Release.

To download the current JDK release, click here.
JDK 11 JDK 12 Other
11 b22Fixed 12Fixed openjdk8u292Fixed
Related Reports
Relates :  
JDK-8257192 - Integrate AArch64 JIT port into 8u
Description
StoreCM may require planting a StoreStore barrier
Comments
A StoreCM node is employed by C2 to provide an opportunity for architectures with weak memory systems to generate a StoreStore barrier before the byte store that implements a card mark. This is needed to ensure that the GC does not miss the chance to scan updated objects. It cannot observe the dirty card before the associated field write is visible. AArch64 omits the StoreStore barrier (dmb ishst) in several cases, one of which is wrong. It correctly omits the store with 2 gc configs +UseG1GC or +UseConcMarkSweepGC +UseCondCardMark because in these two cases the ideal graph includes a MemBarVolatile and this gets translated to str ;; dmb ish ;; strb Adding a dmb ishst before the strb would be redundant. With gc config +UseConcMarkSweepGC -UseCondCardMark AArch64 generates the StoreStore barrier for a non-volatile store str ;; dmb ishst ;; strb However, it mistakenly omits the StoreStore barrier when a volatile store is generated using an stlr instruction: stlr ;; strb This is actually incorrect. An AArch64 CPU may legitimately allow the strb visible before the stlr is visible. AArch64 should always insert a StoreStore barrier between an object filed write and its following card barrier write for this GC config, whether or not the field is volatile.
02-07-2018