JDK-8177817 : Remove assertions in 8u that were removed by 8056124 in 9.
  • Type: Bug
  • Component: hotspot
  • Sub-Component: runtime
  • Priority: P4
  • Status: Closed
  • Resolution: Fixed
  • Submitted: 2017-03-30
  • Updated: 2018-02-08
  • Resolved: 2017-03-31
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JDK 7 JDK 8
7u141Fixed 8u131Fixed
Description
8056124: Hotspot should use PICL interface to get cacheline size on SPARC 
..is already backported to 8u.  However in 9 that change removes some assertions in src/cpu/sparc/vm/vm_version_sparc.cpp, which are not removed in 8u, because they weren't there at the time.

Backporting 8049717 adds an assert in vm_version_sparc.cpp, which will trigger if we backport 8134119 into 8u.

This bug will remove them, and get 8u ready for a straightforward backport of 8134119.
Comments
If we backport 8049717 simply into 8u, we then need to make the following change before backporting 8134119: bash-4.2$ hg diff diff -r 84212a4e67e1 src/cpu/sparc/vm/vm_version_sparc.cpp --- a/src/cpu/sparc/vm/vm_version_sparc.cpp Fri Mar 17 07:52:54 2017 -0700 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Thu Mar 30 03:42:38 2017 -0700 @@ -259,49 +259,6 @@ // buf is started with ", " or is empty _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); - // There are three 64-bit SPARC families that do not overlap, e.g., - // both is_ultra3() and is_sparc64() cannot be true at the same time. - // Within these families, there can be more than one chip, e.g., - // is_T4() and is_T7() machines are also is_niagara(). - if (is_ultra3()) { - assert(_L1_data_cache_line_size == 0, "overlap with Ultra3 family"); - // Ref: UltraSPARC III Cu Processor - _L1_data_cache_line_size = 64; - } - if (is_niagara()) { - assert(_L1_data_cache_line_size == 0, "overlap with niagara family"); - // All Niagara's are sun4v's, but not all sun4v's are Niagaras, e.g., - // Fujitsu SPARC64 is sun4v, but we don't want it in this block. - // - // Ref: UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005 - // Appendix F.1.3.1 Cacheable Accesses - // -> 16-byte L1 cache line size - // - // Ref: UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC - // Section III: SPARC Processor Core - // -> 16-byte L1 cache line size - // - // Ref: Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture - // Section SPARC T4 Processor Cache Architecture - // -> 32-byte L1 cache line size (no longer see that info on this ref) - // - // XXX - still need a T7 reference here - // - if (is_T7()) { // T7 or newer - _L1_data_cache_line_size = 64; - } else if (is_T4()) { // T4 or newer (until T7) - _L1_data_cache_line_size = 32; - } else { // T1 or newer (until T4) - _L1_data_cache_line_size = 16; - } - } - if (is_sparc64()) { - guarantee(_L1_data_cache_line_size == 0, "overlap with SPARC64 family"); - // Ref: Fujitsu SPARC64 VII Processor - // Section 4 Cache System - _L1_data_cache_line_size = 64; - } - // UseVIS is set to the smallest of what hardware supports and what // the command line requires. I.e., you cannot set UseVIS to 3 on // older UltraSparc which do not support it.
30-03-2017