Relates :
|
As discussed in LKML: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html, the cost of changing a cacheline from shared to exclusive state can be significant, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. So it's better to make use of the aarch64 "prfm" instruction to prefetch cachelines for write prior to ldxr/stxr loops.