These changes calculate register pressure at the entry of a basic block, at the end and incrementally while we are scheduling. It uses an efficient algorithm for recalculating register pressure on a as needed basis. The algorithm uses heuristics to switch to a pressure based algorithm to reduce spills for int and float registers using thresholds for each.  It also uses weights which count on a per register class basis to dope ready list candidate choice while scheduling so that we reduce register pressure when possible.  Once we fall over either threshold, we start trying mitigate pressure upon the affected class of registers which are over the limit.  This happens on both register classes and/or separately for each. We switch back to latency scheduling when pressure is alleviated.  As before we obey hard artifacts such as barriers, fences and such.  Overhead for constructing and providing liveness information and the additional algorithmic usage is very minimal, so as affect compile time minimally.