I think when we added this code (6 years ago) for Athlon64 we used line size which could be conservative. In worst case we flashing cacheline 2 times, that is all. But you are right the line size should not be hardcoded at that place but taking from VM_Version code like L1_data_cache_line_size() which is based on cpuid.

Vladimir

Venkatachalam, Vasanth wrote:
> Hi Vladimir,
>
> We are investigating JVM optimizations for Bulldozer hardware. I noticed a file in the Hotspot source src/cpu/x86/vm/icache_x86.hpp that is setting the instruction cache line size to 32B for AMD64. Here���s a snippet of code. For brevity, I���ve stripped away some of the comments:
>
> // Interface for updating the instruction cache.  Whenever the VM modified
> // code, part of the processor instruction cache potentially has to be flushed.
>
> class ICache : public AbstractICache {
>  public:
> #ifdef AMD64
>   enum {
>     stub_size      = 64, // Size of the icache flush stub in bytes
>     line_size       = 32, // Icache line size in bytes
>     log2_line_size = 5   // log2(line_size)
>   };
>
> Maybe I���m reading this incorrectly, but the comments suggest that Hotspot is assuming the icache line size to be 32B, for the purposes of flushing the icache whenever it modifies code. It looks like this information is being used in the file src/share/vm/runtime/icache.cpp, for example, in the invalidate_word( ) method, which is getting called from nativeInst_x86.cpp.
>
> Can you explain why 32 was chosen for line_size in this code? The actual L1 ICache line size is 64B.
>
> Regards,
> Vasanth