JDK-6232485 : ClearArrayNode::Ideal forces use of 32-bit stores for zeroing memory
  • Type: Bug
  • Component: hotspot
  • Sub-Component: compiler
  • Affected Version: 6
  • Priority: P3
  • Status: Resolved
  • Resolution: Fixed
  • OS: solaris_9
  • CPU: sparc
  • Submitted: 2005-02-24
  • Updated: 2011-09-15
  • Resolved: 2005-03-30
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Other JDK 6
5.0u5Fixed 6 b30Fixed
Description
C2 emits unrolled stores for zeroing small constant amounts of memory but it forces the use of 32-bit stores through the use of the StoreI node.  This is clearly wrong on 64-bit platforms and less then optimal on v8plus since we could use stx G0 on niagara where instruction count is king.
###@###.### 2005-2-24 02:22:23 GMT
Comments
SUGGESTED FIX --- memnode.cpp Thu Mar 24 10:37:28 2005 *** 1,12 **** --- 1,12 ---- #ifdef USE_PRAGMA_IDENT_SRC - #pragma ident "@(#)memnode.cpp 1.216 05/03/05 20:34:27 JVM" + #pragma ident "@(#)memnode.cpp 1.217 05/03/24 10:37:27 JVM" #endif /* * Copyright 2005 Sun Microsystems, Inc. All rights reserved. * SUN PROPRIETARY/CONFIDENTIAL. Use is subject to license terms. */ // Portions of code courtesy of Clifford Click // Optimization - Graph Style *** 1135,1165 **** --- 1135,1162 ---- const Type* at = phase->type(adr); if( at==Type::TOP ) return NULL; const TypePtr* atp = at->isa_ptr(); // adjust atp to be the correct array element address type if (atp == NULL) atp = TypePtr::BOTTOM; else atp = atp->add_offset(Type::OffsetBot); // Get base for derived pointer purposes if( adr->Opcode() != Op_AddP ) Unimplemented(); Node *base = adr->in(1); - // It's marginally nicer to write 32-bit chunks instead of 64-bit chunks, - // because it's easier to fold up redundant initialization writes. Node *zero = phase->makecon(TypeInt::ZERO); con <<= 1; // Write words instead of doublewords Node *off = phase->MakeConX(BytesPerInt); mem = new (4) StoreINode(in(0),mem,adr,atp,zero); + Node *zero = phase->makecon(TypeLong::ZERO); + Node *off = phase->MakeConX(BytesPerLong); + mem = new (4) StoreLNode(in(0),mem,adr,atp,zero); con--; while( con-- ) { mem = phase->transform(mem); adr = phase->transform(new (4) AddPNode(base,adr,off)); - mem = new (4) StoreINode(in(0),mem,adr,atp,zero); + mem = new (4) StoreLNode(in(0),mem,adr,atp,zero); } return mem; } //============================================================================= // Do we match on this edge? No memory edges uint StrCompNode::match_edge(uint idx) const { return idx == 5 || idx == 6; } --- sparc.ad Thu Mar 24 10:37:49 2005 --- 5535,5565 ---- instruct storeI0(memory mem, immI0 src) %{ match(Set mem (StoreI mem src)); ins_cost(MEMORY_REF_COST); size(4); format %{ "STW $src,$mem" %} opcode(Assembler::stw_op3); ins_encode( form3_mem_reg( mem, R_G0 ) ); ins_pipe(istore_mem_zero); + %} + + instruct storeL0(memory mem, immL0 src) %{ + match(Set mem (StoreL mem src)); + ins_cost(MEMORY_REF_COST); + + size(4); + format %{ "STX $src,$mem" %} + opcode(Assembler::stx_op3); + ins_encode( form3_mem_reg( mem, R_G0 ) ); + ins_pipe(istore_mem_zero); %} // Store Integer from float register (used after fstoi) instruct storeI_Freg(memory mem, regF src) %{ match(Set mem (StoreI mem src)); ins_cost(MEMORY_REF_COST); size(4); format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} opcode(Assembler::stf_op3); ###@###.### 2005-03-24 18:50:59 GMT ###@###.### 2005-03-25 00:35:54 GMT
24-03-2005
EVALUATION Initial tests show that storeI is faster than storeL on a USII, I'm going to find a Niagara box and see if there is a difference there. ###@###.### 2005-03-17 22:17:28 GMT Code was incorrect, its faster to use StoreL than StoreI ###@###.### 2005-03-17 23:20:09 GMT
17-03-2005