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Bug ID: JDK-6797305 Add LoadUB and LoadUI opcode class
JDK-6797305 : Add LoadUB and LoadUI opcode class

Details
Type:
Enhancement
Submit Date:
2009-01-23
Status:
Resolved
Updated Date:
2010-07-29
Project Name:
JDK
Resolved Date:
2009-03-18
Component:
hotspot
OS:
solaris_9,generic,solaris_10,windows_xp
Sub-Component:
compiler
CPU:
x86,sparc,generic
Priority:
P5
Resolution:
Fixed
Affected Versions:
hs15,5.0,5.0u4,6,7
Fixed Versions:
hs15 (b03)

Related Reports
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Sub Tasks

Description
Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher.

These classes will handle code like, e.g.:

bytearray[i] & 0xFF
intarray[i] & 0xFFFFFFFF

                                    

Comments
PUBLIC COMMENTS

While implementing LoadUI2L I noticed that it does not make much sense to add that one.

On x86_64 there is no such instruction to do that load, because loading an E-register clears the high bits implicitly anyway.  And on SPARC all integer loads are unsigned integer loads.
                                     
2009-02-02
EVALUATION

Some micro benchmarks show a big performance win.
                                     
2009-02-24
PUBLIC COMMENTS

I have to revert that.  On 32-bit x86 the LoadUI2L opcode helps a lot.
                                     
2009-02-24
PUBLIC COMMENTS

Please note that SPARC has signed loads (which sign-extend into the 64-bit
integer registers) for byte, short, and int.  They are: LDSB, LDSH, LDSW.
SPARC also has unsigned loads (which zero-extend): LDUB, LDUH, LDUW.
Of course, SPARC also has a 64-bit load: LDX.
                                     
2009-02-27
PUBLIC COMMENTS

All these instructions are used in my changes.
                                     
2009-02-27
EVALUATION

http://hg.openjdk.java.net/jdk7/hotspot-comp/hotspot/rev/337400e7a5dd
                                     
2009-03-09
EVALUATION

@brackeen: Well the only thing I can think of (for x86) is to use partial register moves (using MOVZX instructions instead of SHR-AND sequences), e.g.:

  int g = (anInt >> 8) & 0xff;

  MOV    EBX,ECX
  SHR    EBX,#8
  AND    EBX,#255

vs.

  MOVZX8 EBX,CH

or:

  int b = anInt & 0xff;

  MOV    EBX,ECX
  AND    EBX,#255

vs.

  MOVZX8 EBX,CL

While the latter one is likely to have the same performance, as the resulting micro instructions should be the same.  I will run some tests.  Do you have a use-case you can send me?
                                     
2009-09-21



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