JDK-6660833 : [1.4.2] : 2 incorrect right shift operation in compiler2 in 1.4.2(Itanium2)
  • Type: Bug
  • Component: hotspot
  • Sub-Component: compiler
  • Affected Version: 1.4.2_16
  • Priority: P3
  • Status: Closed
  • Resolution: Duplicate
  • OS: linux_redhat_3.0
  • CPU: itanium
  • Submitted: 2008-02-08
  • Updated: 2010-08-04
  • Resolved: 2008-03-12
Related Reports
Duplicate :  
Description
The customer reported  2 possible problems in shift operation in compiler2.

CONFIGURATION :
OS : Red Hat Enterprise Linux Server release 5 (Itanium)
     Red Hat Enterprise Linux AS release 4 (Itanium)
JDK : 1.4.2_14 / 1.4.2_16 Server VM

1. unsigned right shift operation and shift distance is more than 32 

1.4.2_16/hotspot/src/cpu/ia64/vm/ia64.ad:
.....
  3363    enc_class emit_shruI_reg_imm6( gRegI dst, gRegI src, gRegI cnt, pReg qp ) %{
  3364      MacroAssembler _masm(&cbuf);
  3365      if ( (int)$cnt$$constant < 32 )
  3366        __ extru( as_PredicateRegister($qp$$reg), as_Register($dst$$reg), as_Register($src$$reg),
  3367                  (int)$cnt$$constant, 32 - (int)$cnt$$constant );
  3368      else
  3369        __ extru( as_PredicateRegister($qp$$reg), as_Register($dst$$reg), as_Register($src$$reg), 31, 1 );
  3370    %}
....

At line#3369, the following code is generated.

  0x2000000005b64a12:             extr.u r48=r49,31,1;;

  left-hand operand is positive number : the result is always 0.
  left-hand operand is negative number : the result is always 1.

2. signed right shift operation and shift distance is more than 32 

1.4.2_16/hotspot/src/cpu/ia64/vm/ia64.ad:
.....
  3383    enc_class emit_sarI_reg_imm6( gRegI dst, gRegI src, gRegI cnt, pReg qp ) %{
  3384      MacroAssembler _masm(&cbuf);
  3385      if ( (int)$cnt$$constant < 32 )
  3386        __ extr( as_PredicateRegister($qp$$reg), as_Register($dst$$reg), as_Register($src$$reg),
  3387                 (int)$cnt$$constant, 32 - (int)$cnt$$constant );
  3388      else
  3389        __ extr( as_PredicateRegister($qp$$reg), as_Register($dst$$reg), as_Register($src$$reg), 31, 1 );
  3390    %}
.....

At line#3389, the following code is generated.

  0x2000000005b64a12:             extr r48=r49,31,1;;

  left-hand operand is positive number : the result is always 0.
  left-hand operand is negative number : the result is always -1.

Comments
EVALUATION We have agreed to duplicate this with 6654460, they are basically the same issue in the ia64.ad assembly macros, but this CR talks about right shifts, and that CR handles left shifts. We have the customer's fix suggestion and are testing it, will close this CR and handle the integration through 6654460.
12-03-2008